Abstract
Membrane projection lithography (MPL) is proposed as a method for creation of 3-dimensional integrated circuits at the device level as opposed to stacking 2-D die. In MPL, standard semiconductor fabrication processes and equipment are used in a novel sequence of processing steps to create 3 dimensional micrometer-scale structures. Generalization of MPL from strictly deposition to ion implantation and dry etching, combined with blanket processes such as CVD deposition and oxidation, provide all the necessary ingredients for fabrication of integrated circuit devices in all three coordinate axes in high topography silicon.
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