Abstract
A voltage latch sense amplifier by applying the power consumption reduction method is introduced. The presented sense amplifier is compared with the classical volt¬a¬g¬e latch-type sense amplifier and an amplifier with a leakage control (LECTOR) technique is applied. The designs are carried out by 14 nm FinFET technology. The resu¬l¬t¬s of simulations show that in the case of the proposed design, the power dissipation and propagation delay is improved. Simulation is performed for typical-typical (tt), slow-slow (ss), and fast-fast (ff), process voltage temperature (PVT) corners.
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