Analysis of Low Power SRAM Sense Amplifier

Abstract

Rapid increase in technology for faster and smarter innovations that smoothens the needs of humans resulting in use of super tech gadgets, which use memory, such as, SRAM. In the present time we want that the data to be written and Read from SRAM at very high speed and with low power consumption. Sense Amplifier is the key circuit used for reading the data in memory. The major issue in modern integrated circuit design is power consumption which is an important parameter to design memory element and digital system. In this work we have analyzed the 6T SRAM by using different sense amplifiers namely Foot Switch PMOS Access Voltage Latch Sense Amplifier (FSPA-VLSA), Current Latch Sense Amplifier (CLSA) & Voltage Latch Sense Amplifier (VLSA) in terms of power. Furthermore, comparison of CLSA and VLSA in terms of power, area, delay, power delay product (PDP) and static noise margin has been performed. In this paper, several latch type sense amplifiers have been analyzed and simulated using 45nm CMOS technology with supply voltage of 1.2V. The simulation results show that when this technique is applied with SRAM circuit during read operation, overall power consumption has been reduced. The overall power consumption has been reduced to approximately 20.63% whereas in case of Current Latch and Voltage Latch Sense Amplifier it is up to 10.37% and 2.37%respectively and the delay of SRAM FSPA has been reduced by 243.8%. Also, the static power consumption in SRAM with body bias technique has been reduced by91%. As the body biasing of transistor will lead to a decrement in leakage of the device, hence the static power consumption.