Abstract
In this paper, an improved method for determining the gate-bias dependent source and drain series resistances RD and effective channel length Leff=LM−ΔL (LM is the mask channel length and ΔL is the channel length reduction) of advanced MOS devices is developed for the purpose of providing a better accuracy for the modeling of the current–voltage characteristics of LDD MOSFETs operating from 25 to 120°C. Our results show that both ΔL and RSD decrease with increasing gate-bias, but increase with increasing temperature. In addition, the gate-bias dependence of ΔL and RSD becomes weaker as the temperature rises. Experimental data obtained from devices fabricated using the 0.14 and 0.09μm DRAM technologies are included in support of the theoretical work developed.
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