Design of reed-solomon encoder/decoder using modified euclid's algorithm

Abstract

Reed-Solomon (204, 188) encodeddecoder was designed on Xilinx FPGA for the application of communication system. This decoder corrects the symbol errors up to eight symbols. It employs a modified Euclid's algorithm to compute the error locator polynomials and error evaluator polynomials of input data. The proposed architecture of RS Decoder has the following features. The circuit size is reduced by applying a modified Euclid's algorithm. Only one Euclid's cell is necessary for mutual process. And the processing rate of decoder.is improved by using ROM and parallel structure. The RS decoder designed in this paper can be used as an LF' library for communication system. The proposed encoder/decoder is simulated with ModelSim and synthesized with Synopsys. When the chip is implemented on Xilinx Vertex XCVSOO. The number of gates is about 60,000. The RS code is the error correction code included in standard for the IMT-2000 and B-WLL.