<title>VLSI Reed-Solomon decoder</title>

Abstract

ABSTRACT In this paper, a VLSI architecture for Reed-Solomon (RS) decoder based on the Berlekamp algorithm is proposed. The proposed decoder provides both erasure and error correcting capability. In order to reduce the chip area, we reformulate the Berlekamp algorithm. The proposed algorithm possesses a re-cursive structure so that the number of cells for computing the errata locator polynomial can be reduced.Moreover, in our approach, only one finite field multiplication per clock cycle is required for implementa-tion, provided an improvement in the decoding speed. And the overall architecture features parallel andpipelined structure, making a real time decoding possible. It is shown that the proposed VLSI architec-ture is more efficient in terms of VLSI implementation than the architecture based on the recursive Euclidalgorithm. 1. INTRODUCTION Recently, much efforts have been focused on the digital processing of video signals. Digital video tech-nology has many application areas, such as a high definition television (HDTV) or digital VTR. However,when the digital signals are transmitted through a channel or recorded in a storage device, the received orreplayed digital data are sometimes corrupted with errors caused by noise, dusts or fingerprints. Hence, itis indispensable to employ an error control code in the digital video communication or recording system.In the literatures1'2'3, a variety of error control codes can be found. Among the various error control codes,the Reed-Solomon (RS) code has gained a popularity since the RS code is known to provide a good errorcorrecting capability for both the random and burst errors. The RS encoder can be easily implemented us-ing the shift registers. However, in the RS decoder, obtaining an error locator polynomial, which providesthe information for the error location, is the most complicated and time-consuming procedure. Since thedecoding process requires for solving simultaneous equations1, which, in fact, requires for a large amountof computations, many simple and iterative algorithms have been introduced1'2 so far. Among them, boththe Euclid algorithm and the Berlekamp algorithm are known to be popular techniques. Recently, severalworks related to the VLSI implementation for the RS decoder have been reported4'5'6'78'9. Because ofthe rapid development in the VLSI technology, the availability of low-cost, high-density fast VLSI devicemakes high speed implementation of complicated algorithms practical and cost-effective. Liu4 proposed aVLSI architecture for RS decoders based on the Berlekamp algorithm. On the other hand, Shao5 also pro-posed a VLSI architecture for RS decoders based on the Euclid algorithm. Later, in an effort to reduce thearea complexity, Shao proposed an improved architecture by introducing the modified Euclid algorithm6.The main idea of the architecture in Ref. 6 is that, instead of using the multiple cells simultaneously, therecursive use of the cells could reduce the area complexity. However, it appears that the required chip areais still large for a practical application. Thus, the development of the VLSI architecture which requiresless chip area would be still an interesting problem.It is noted that in the Euclid algorithm, the number of updated coefficients equals to the maximum