A VLSI implementation of a low complexity Reed-Solomon encoder and decoder for CDPD

Abstract

This paper presents VLSI implementation of an area efficient 8-error correcting (63,47) Reed-Solomon(RS) encoder and decoder for the CDPD (cellular digital packet data)communication systems. We implement this RS decoder using Euclidean algorithms which are regular, simple and naturally suitable for VLSI implementation. Constant multipliers based on certain composite fields are deployed in the encoder, which significantly decreases the encoder's area. Multipliers over a certain composite field GF((2)2) adopted in this paper lower the complexity of the multiplication of the decoder. The RS encoder and decoder can independently operate at a clock frequency of 30 MHz. This chip was fabricated in 0.6/spl mu/m CMOS 1P2M technology with a supply of voltage of 5V, with die area 4mm /spl times/ 4mm. The chip has been fully tested and stratifies the demand of the CDPD communication systems.