Design of an area efficient Reed-Solomon decoder ASIC chip

Abstract

We describe an area efficient pipelined Reed-Solomon (RS) decoder. We propose two simple basic cell architectures which evaluate the error locator and the error magnitude polynomial in the general Euclid's algorithm. The evaluation involves high computational complexity, and thus, it affects the speed and the hardware complexity of RS decoders. The proposed architectures can reduce the hardware complexity by more than 16% of existing RS decoder architectures. The proposed RS decoder can be programmed to decode four RS codes defined in Galois field 2/sup 8/, i.e., (200, 188), (120, 108), (60, 48), and (40, 28) and can correct up to six errors. The fabricated FEC (Forward Error Correction) chip including the RS and Viterbi decoders operates at 40 MHz. The total number of gates for the RS decoder is about 31,000 and the FEC chip contains about 76,000 gates.