Design of Low-power Quad-edge-triggered Flip-flop at Switch Level

Abstract

This paper presents a novel approach to design quad-edge-triggered flip-flop (QETFF) based on ternary clock. At first, the previous QETFF consisting of 3-to-1 multiplexers is reviewed and analyzed; the property of ternary clock is pointed out. By using it, a novel multiplexer is proposed, following which a novel design of QETFF named after uQETFF is proposed, of which the circuit is simpler than the previous one, saving 8 transistors. Then, HSPICE simulations with TSMC 180 nm CMOS technology are carried out on the proposed uQETFFs, their ideal logic functionality being shown. At last, performance comparisons between the proposed uQETFFs and its equivalent flip-flops are made. From the comparisons, it can be seen that the proposed binary uQETFF consumes 13.6% less energy than the equivalent double-edge-triggered flip-flop (DETFF) based on binary clock; the proposed ternary uQETFF optimizes the overall circuit performance with a reduction of 43.5% in PDP (power-delay product) compared to the previous ternary QETFF. Therefore, the proposed uQETFFs are simpler and their characteristics are more desirable, which are more close to the requirements of the practical applications.