Design of Low Power Transmission Gate Based 9T SRAM Cell

S Rooban,R Manimegalai,Moru Leela,N Subbulakshmi,Md Zia Ur Rahman

doi:10.32604/cmc.2022.023934

Abstract

Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energy-consuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG-ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively.

Highlights

As technology evolves each day, the important design constraints for transistor scaling are the speed and integrated density, while leakages and reliability issues degrade the overall device performances
The implementation results of the proposed TG Schmitt trigger (ST)-9T are compared with other static random-access memory (SRAM) cells using 45-nm CMOS technology
Monte Carlo simulations are performed in HSPICE to evaluate the SRAM cell design

Summary

Introduction

As technology evolves each day, the important design constraints for transistor scaling are the speed and integrated density, while leakages and reliability issues degrade the overall device performances. Electronic devices, like microprocessors and microcontrollers, require high performances based on low power and high speeds. Such devices may be packed compactly and handled but require a memory cell with a low power consumption [2,3]. In the sub-threshold region, the gate-to-source voltage is not as high as the edge voltage of a MOSFET, so this region is called the cut-off region where the effects of current on the gate voltage are exponential. In the super threshold region, the gate-to-source voltage is greater than the MOSFET threshold voltage and is called the saturation region as there is no effect on the current with a greater drain voltage [9]

Methods

Results

Conclusion