Abstract
In this paper design and simulation of a 10 GHz, divide‑by‑16…511 programmable frequency divider based on ETSPC and TSPC logic flip-flops in 65 nm CMOS are presented. Main blocks of the divider are three-stage dual modulus divide by 2/3 divider chain, 6-bit counter, jitter removal and synchronisation flip-flops. Extended True Single Phase Clock (ETSPC) logic is used for 2/3 dividers to achieve high input frequency and low power and TSPC logic is used for 6-bit counter. Simulation of the divider was made using Cadence software. Divider’s operation frequency is up to 10 GHz. Resulted phase noise is -143.7 dBc/Hz at 1 kHz offset from output frequency and power dissipation is 29.35 mW when input frequency is 10 GHz, division ratio is set to 23, supply voltage 1.2 V. The main application of such divider is as feedback divider in frequency synthesizer for wireless communication systems.DOI: http://dx.doi.org/10.5755/j01.eee.19.6.4570
Highlights
Major challenges for advanced communication circuit designs are high speed, low phase noise and low power consumption
In this paper we propose novel programmable divide-by-16...511 frequency divider based on Extended True Single Phase Clock (ETSPC) and TSPC logic flip-flops in 65 nm CMOS technology
Division ratio is set to 23 to check if all 2/3 prescalers operate correctly – this is the hardest operation condition, with highest input frequency and lowest division ratio at which all 2/3 prescalers are set to divide by 3 mode
Summary
Major challenges for advanced communication circuit designs are high speed, low phase noise and low power consumption. In frequency synthesizer output signal of the voltage controlled oscillator (VCO) is input signal for feedback divider. It operates at highest chip frequencies, what results in increased power consumption, which should be as low as possible for mobile communication devices. In early CMOS frequency dividers flip-flops based on Razavi topology [1] was used to achieve high frequencies. CMOS technology scaling allowed usage of low power TSPC flip-flops to achieve required frequencies. In this paper we propose novel programmable divide-by-16...511 frequency divider based on ETSPC and TSPC logic flip-flops in 65 nm CMOS technology. Resulted design and simulation with input frequency up to 10 GHz are presented
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