Design of Five Port Router for 3x3 Mesh Network Using Verilog

Abstract

With technological advancements, a large number of intellectual property (IP) cores can be integrated into a single chip. As a result, communication between these cores is critical. Such communication is achieved using Network on Chip (NoC) technology. NoC is an on-chip packet-switched network with IP cores connected to the network via interfaces, and packets are sent to their destinations via a multi-chip routing path. A router is the essential component of the NoC architecture, it must be designed efficiently to build a competitive NoC architecture. Verilog is used to design the router which supports five parallel connections. It uses store and forward type of flow control, round-robin arbitration, and deterministic XY routing. The building blocks of the router are FIFO, arbiter, and crossbar. The proposed architecture of the five port router is targeted to the Spartan 6 XC6SLX45 FPGA design platform and simulated in Xilinx ISE 14.5 software.