VHDL Implementation of NOC Architecture for UART Using Round Robin Arbiter

Abstract

In this design, we have introduced a NOC architecture for UART using Round Robin Arbiter. NOC (Network on a chip) is a communication subsystem on an integrated circuit between intellectual property (IP) cores in a system on chips (SOC). NOC is a newly developed method for solving problems that challenge system on chip (SOC) for on a chip communication. NOC is considered as the best solution for avoiding problems which occur because of the growing size of the chip. The proposed method adopts a round robin arbiter and three UARTs. This design uses Arbiter to control the arbitration of the ports and resolve contention problem where, so many requestors want to access the same output port. Three UART modules are used and the inputs and outputs of the UART’s are considered as input and output ports for the NOC architecture. The outputs of arbiter i.e. grant signals are used as select lines of Multiplexer in this design. Designed NOC Architecture reduces the device utilization as compared to Basic NOC Architecture. Also designed NOC Architecture with Arbiter reduces the memory usage as compared to the Architecture without Arbiter. The designed Round Robin Arbiter should be fair, no starvation, and should provide high throughput.