Design of clock and data recovery system’s behavioral model for high speed transceivers of serial interfaces

Alexey V Dubinskiy,Nikolay Yu Rannev,Denis A Domozhakov,P Yermolov

doi:10.1051/itmconf/20193003013

Alexey V Dubinskiy, Nikolay Yu Rannev + Show 2 more

Open Access

https://doi.org/10.1051/itmconf/20193003013

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Abstract

This paper provides a parameterizable behavioral model of a clock and data recovery system (CDR) based on phase-locked loop (PLL) for the receiver part of a high-speed serial interfaces. The model was used to calculate parameters and characteristics of the system as well as estimate their calculation error depending on the sub-circuit characteristics taken into account. A model structure was selected based on the obtained jitter estimation error. The model complies with all the accuracy and speed requirements to calculations of the characteristics of a PLL-CDR system for a receiver block with data transmission bit rates above 3.125 Gbit/s.

Highlights

The system of Clock and Data Recovery (CDR) is an integral part of high-speed transceivers of serial interfaces
A CDR system based on a phase-locked loop (PLL) circuit with a “bang-bang” phase detector [1] is a common type of CDR system architecture [2]
Behavioral models require, firstly, estimation of the calculation error because they do not take into account all the characteristics of electric circuits of the reference model; and secondly, determination of a set of parameters to take into account to achieve an acceptable calculation error

Summary

Introduction

The system of Clock and Data Recovery (CDR) is an integral part of high-speed transceivers of serial interfaces. High-level behavioral models have gained widespread use at the stage of PLL-CDR system characterization. A behavioral model uses parameters of certain sub-circuits of the transistor model, which enables highly accurate calculations at the stage of behavioral modelling of the system. Behavioral models require, firstly, estimation of the calculation error because they do not take into account all the characteristics of electric circuits of the reference model; and secondly, determination of a set of parameters to take into account to achieve an acceptable calculation error. The paper estimates the error of parameters calculation performed using the PLL-CDR behavioral model and the influence of sub-circuit parameters and characteristics on the error. A behavioral model of PLL-CDR system for a receiver with the bit rate of 3.125 Gbit/s was developed using Verilog-AMS hardware description language followed by a comparison with the reference model

Main parameters and characteristics of the system

Sub-circuits of the system and their parameters

Error estimation of the behavioral model

Findings

Conclusion