A 9-10.8 Gb/s Linear Clock and Data Recovery System with Adaptive Loop Gain

Abstract

This paper presents a linear high capture range clock and data recovery (CDR) system with adaptive loop gain in 180 nm CMOS. The high capture range of the CDR is achieved by a Hogge phase detector which exploits an adjustable strobe point that varies the control voltage to get locked. The loop bandwidth of the system varies automatically for better jitter transfer without jitter peaking increasement. The proposed system operates from 9 to 10.8 Gb/s and its loop bandwidth varies from 7.5 MHz to 2.7 MHz which improves jitter transfer by 11.87 dB. The random jitter of the recovered data is $\pmb{0.486 \mathbf{ps}_{\mathbf{rms}}}$ at BER of $\pmb{10^{-12}}$ .