Novel Decimation Topology with Improved Jitter Performance for Clock and Data Recovery Systems

Abstract

This paper discusses the effect of the decimation topology on the jitter performance of Bang-Bang phase detector-based digital Clock and Data Recovery (CDR) systems. It compares the jitter performance of the most common decimation topologies for a fixed input jitter power. A new decimation topology is also proposed to help decouple the transferred jitter (JTRAN) and the generated jitter (JGEN) from the CDR jitter tolerance (JTOL). The jitter performance of the newly proposed decimator has been verified with a MATLAB/simulink model of the CDR.