Power and noise configurable phase-locked loop using multi-oscillator feedback alignment

Abstract

A 16-phase phase-locked loop (PLL) suitable for a 25 Gb/s, 1/8th rate clock and data recovery (CDR) system is presented. Sub-rate CDRs have been shown to be reconfigurable to operate at fractions of their peak data rate. When operating at less than the maximum data rate, power dissipation can be reduced. Also, the jitter that can be tolerated from the multi-phase PLL is higher, suggesting a desirable power/jitter trade-off for power minimization across data rates. This PLL allows for on-the-fly trading off of power dissipation versus jitter performance by dynamically connecting between one and three identical sub-VCOs together to generate its 16 output phases. To minimize sudden phase excursions during VCO reconfiguration, a power-on sequence and a variable-capacitance load have been used. Simulation results using TSMC 65 nm show that the power dissipation reduces by 57% when switching from three to one VCO. Alternatively, the jitter can decrease by a factor of 1.5x when the PLL is reconfigured from one to three VCOs. This can be done with a maximum absolute timing excursion of 16 ps, making it suitable for an on-the-fly reconfiguration of the CDR from 12.5 to 25 Gb/s.