Abstract
Since the Programmable Logic Arrays (PLAs) can implement almost any Boolean function, they have become popular devices in realization of both combinational and sequential circuits. We present a power‐saving fast half swing CMOS circuit implementation for NOR–NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced. Detailed simulation results reveal appropriate L/W guidelines. The analysis of effects of the 1/2 VDD on power and speed is also provided in this work.
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