Design of a Quaternary Component and Wallace Tree Integrated Baugh-Wooley Multiplier

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Modifying a single hardware component can have a profound effect on the system's claimed speed, power consumption, and synchronized and parallel functionality. An integral part of these digital circuits and systems is the multiplier. Carry look-ahead (CLAs) adducts are low-power components used by researchers with various enhancements to reduce latency and power consumption. The Baugh Wooley multiplier is a well-known multiplier that incorporates CLA. In this paper, we present an enhanced design for this multiplier. By incorporating a carry look-ahead adder based on Quaternary logic, this work improved the structural behavior of the Baugh Wooley Multiplier. In this design, the Wallace Tree algorithm was used to optimize the functionality. For use with 180 nm technology and requiring only 1.8 w of power, this proposed improved Baugh Wooley multiplier was developed. The CLA Multiplier, QSDCLA (Quaternary Signed Digit-based Carry Look Ahead) Multiplier, Baugh Wooley Multiplier, Wallace Tree Multiplier, Hasan Multiplier, and Improved Radix Adder are compared to the proposed architecture. We used latency and energy use as our metrics of evaluation. The latency time was reduced to 0.0008962 ns, and the power consumption was reduced by 1.693 w with the proposed architecture. The results show that the new multiplier is significantly more effective and reliable than the previous multipliers.