Design of a high-speed Reed-Solomon decoder

Abstract

This paper proposes a Reed-Solomon (RS) decoder for applications that require high-speed data communication and reliability. The proposed architecture can support variable n and k values (37<n/spl les/255, 21<k/spl les/239). The RS decoder corrects up to eight symbol errors, i.e., t=8. It employs a modified Euclid's algorithm, the Chien search and Forney's algorithms using a systolic array and parallel processing architectures. The proposed Euclid block requires a latency of 2t+1 clock cycles. This architecture reduces latency by about 72% compared with an existing architecture which requires 3t+37 clock cycles when t=8. The decoder operates at 80 MHz and its data transfer rate is 640 Mbps. The proposed decoder has been modeled using the Samsung 0.5 /spl mu/m SOG cell library (KG80) with a supply voltage of 3.3 V.