Design of 7T sram cell for low power applications

Abstract

As the technology of memory on Systems-on-Chip (SoC) is shrinking, the compact devices and embedded systems are emerging, so the low power consumption is very essential for the VLSI system design. Static Random Access Memory (SRAM) contains more than 70% area of the SoC. A standard 6T SRAM cell has two bitlines for read and write operation thus it consumes more power. There are many techniques for power reduction like scaling of supply voltage (VDD) and threshold voltage (Vt), multi- VDD, multi- Vt etc. Scaling of voltages affects adversely on the stability of the SRAM cells. In this paper a dual-Vt 7T (seven transistor) SRAM cell is proposed and compared with the standard 6T SRAM cell on the basis of read delay, write delay, leakage power consumption and Static Noise Margin (SNM) (during hold, read and write). This proposed cell uses single bitline for read and write operation. Thus it also improves the access time of the cell. The consumption of leakage power is reduced by 61.50%. Write delay is reduced by 66.67%. All the simulation work is carried out using the Eldo SPICE tool of Mentor Graphics on 65nm technology at 27°C.