Design and Simulation of 16x16 Vedic Multiplier using Kogge-Stone Adder

Abstract

In terms of applications, chip technology is now growing quite quickly. Even though the use of chips has increased, there are still drawbacks like delay and chip complexity. Kogge-Stone Adder is sufficient to increase speed by acting as compressors (3:2 compressors) in static CMOS, but the demand for chips is driving toward fast computations, which are only possible by the fast multipliers. To increase the speed of multiplication, parallel adder arrays are used to add partial products i.e., Kogge-Stone Adder. In real-time signals and image processing, Vedic multipliers are employed. Multipliers are significant building blocks in digital systems and are essential to the success of digital designs. Multiplication is the essential calculating process in digital systems, and in this study, we analyze the 16x16 Vedic Multiplier architecture using the Kogge-Stone Adder. By increasing the width of the transistor at the current stage, the delay can be reduced. The Vedic multiplier's speed will be increased, and the delay that results from utilizing the half-adder and full adder will be minimized. Therefore, the Kogge-Stone Adder is crucial in this kind of situation for reducing the chip's complexity and delay.