Design of low power barrel shifter and vedic multiplier with kogge-stone adder using reversible logic gates

Abstract

The modern systems are denser and faster. But these systems consume more power. The variants of power dissipation are dynamic power, leakage power, short circuit power and static power dissipation. Adders, Shifters and Multipliers are the essential building blocks of any Digital Signal Processor (DSP) architecture. Hence design of these building blocks to dissipate less power is of utmost importance in digital system design. In order to reduce this power dissipation, there are many low power approaches such as Multi-Vth, reducing the voltage swing, clock gating, use of reversible logic gates etc. The main advantage of designing circuit using reversible logic gates is that the designed circuits will be compatible with the available resources. Reversible Logic gates are that logic gates which have the same number of inputs and outputs and all the outputs are unique for a given input combination. These gates are used to reduce the power dissipation due to loss of information bits. The functional verification of the conventional and reversible Kogge-stone Adder, Vedic Multiplier and Barrel Shifter is performed using Verilog in Xilinx ISE and the power, delay and area of the Kogge-stone Adder, Vedic Multiplier and Barrel Shifter are computed using Cadence RTL compiler software in 90 nm technology. The proposed reversible Vedic Multiplier consumed 0.621 % less power than the conventional Vedic Multiplier. The power dissipation of reversible Barrel Shifter is found to be 26.49 % less than conventional Barrel Shifter.