Design of an Area Efficient Braun Multiplier using High Speed Parallel Prefix Adder in Cadence

Abstract

Matrix multiplication is one of the most fundamental part of digital signal processing systems and is also used as a recursive routine in many signal processing and computational problems. The circuit complexity mainly depends on the multiplication count required for developing the system. Parallel array multiplier is the solution for achieving high execution speed demands. A conventional Braun multiplier includes an array of 16 AND gates, 9 Full Adders, and a ripple carry adder (RCA) in the final stage. A new design of Braun replaces RCA with Kogge-Stone Adder (KSA) for performing faster multiplication. Two designs of KSA are proposed using 14T XOR and 12T XOR gates. A conventional Braun multiplier and Braun multiplier with KSA are designed in cadence Virtuoso tool for 180nm technology with 1.8V source. It is observed that the area reduces by 258 transistors and delay is decreased by 4.65 ns.