Implementation of an efficient multiplier using the vedic multiplication algorithm

Abstract

This paper proposes the implementation of an ancient Indian Vedic multiplier using the 16 bit modified carry select adder, 16 bit ripple carry adder and 16 bit kogge stone adder. The modified carry select adder shows the improved speed performance with less time delay. The design has been implemented using Verilog hardware description language. The design code is tested using the Modelsim simulator. The code is synthesized using Virtex-7 family. The Virtex-7 family is based on 28nm design which has 50 percent lower power compared to the previous generation Virtex-6. The paper makes a comparison of the performance of 16 bit Vedic multiplier using three different adders modified carry select adder, ripple carry adder and kogge stone adder. Results shows that the 16 bit Vedic multiplier using modified carry select adder is better in terms of power consumption and speed as compared to the other two 16 bit Vedic multipliers.