Abstract
A design procedure for sizing all devices in multi-input BiCMOS gates is presented. The notion of an equivalent inverter is introduced, and the optimal ratio of P to N MOSFETs in this inverter is observed to be a constant dependent only on the technology. The bipolar junction transistors (BJTs) are optimally sized for all multi-input gates using data generated only once for the equivalent inverter. Conventional BiCMOS, BiNMOS and CMOS gates are compared in the context of technology scaling. The conventional BiCMOS gate has a 1.4* advantage over CMOS for V/sub dd/ as low as 3.1 V when scaled 0.4- mu m devices are used. The BiNMOS gate overcomes the limitation to further scaling of the conventional gate and shows a 1.23-1.45* advantage over CMOS even for 0.25- mu m, 2.5-V technology. >
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