A 190 ps 0.5 mu m mixed BiCMOS/CMOS channelless gate array family

Abstract

A mixed BiCMOS/CMOS channelless gate array family with three-metal-layer wiring using a 5 V version, 0.5 mu m BiCMOS technology is discussed. The speed and power performance of CMOS gates are superior to those of BiCMOS gates for light load capacitance. Therefore, by using CMOS and BiCMOS gates selectively according to the weight of the capacitance load, the performance of the BiCMOS gate array is enhanced. A novel mixed BiCMOS/CMOS basic cell structure which can be used as BiCMOS or CMOS gates was developed. The area efficiency of the developed basic cell is 16% better than that of the conventional basic cell. The wiring method of the power supply reinforcement lines of the third metal layer in a large chip was examined from the viewpoint of the number of useful basic cells. As a result, by locating the reinforcement lines at every basic cell, the number of useful basic cells is about 14% greater than that of another method in which the reinforcement lines are located at intervals of some basic cells. The propagation delay time of the two-input NAND is 190 ps at fanout 10 load. Under a light load, a pure CMOS NAND is faster, achieving 140 ps gate delay at fanout two load. >