Abstract
The following results have been obtained by evaluating the circuit delay times of submicron BiCMOS, CMOS, and ECL gates by the same criterion: (1) analytical relationships to represent the delay time of each circuit by device parameters have been developed; (2) these relationships have been verified by the circuit simulator using BiCMOS device parameters with minimum dimension of 0.5 μm; (3) using submicron devices for each circuit, the delay time ratio of CMOS, BiCMOS and ECL is 4:2:1; (4) reduction of the device parasitic capacitance is more effective in improving BiCMOS gate delay than that of CMOS gate; and (5) reduction of the parasitic capacitance can make the BiCMOS gate operate as fast as the ECL gate.
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