Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits

Abstract

This paper presents a method for optimizing BiCMOS logic networks that exploits the fact that such networks may use a mixture of both CMOS and BiCMOS gates. The method assumes a given network architecture and finds both the logic family and size for each gate so that total delay (power) is minimized subject to a power (delay) constraint. The method views a BiCMOS gate as a type of buffered CMOS gate and selects the logic family for each gate based on a sequence of gate/buffer sizing optimizations each formulated as a polynomial program. Thus, a high drive BiCMOS gate with a low fan-out can be identified and replaced with a lower power CMOS gate. For a 0.8 /spl mu/m BiCMOS process, an optimized mixed CMOS/BiCMOS 8-bit adder (8 /spl times/ 8 bit multiplier) is found to be up to 21% (17%) faster than the optimized CMOS version dissipating the same power.