Abstract
An analog delay and buffer chip has been designed and built in 1.2 μm CMOS technology to be used in silicon detectors at LHC. Measurements on the performance of the prototype chip are presented. The storage cells variations are smaller than 0.65 rms mV, i.e. 1 100 of the signal in its input for a minimum ionizing particle.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
