Abstract
For the High-Luminosity upgrade of the Large Hadron Collider an increased instantaneous luminosity of up to 7.5 ⋅ 1034 cm−2 s−1, leading to a total integrated luminosity of up to 3000 fb−1, is foreseen. The current silicon and transition radiation tracking detectors of the ATLAS experiment will be unable to cope with the increased track densities and radiation levels, and will need to be replaced. The new tracking detector will consist entirely of silicon pixel and strip detectors. In this paper, results on the development and tests of prototype components for the new silicon strip detector in the forward regions (end-caps) of the ATLAS detector are presented. Flex-printed readout boards with fast readout chips, referred to as hybrids, and silicon detector modules are investigated. The modules consist of a hybrid glued onto a silicon strip sensor. The channels on both are connected via wire-bonds for readout and powering. Measurements of important performance parameters and a comparison of two possible readout schemes are presented. In addition, the assembly procedure is described and recommendations for further prototyping are derived.
Highlights
- The ITk Strip Tracker for the phase-II upgrade of the ATLAS detector of the HLLHC A
Silicon-detector modules are glued for routing on top of a bus tape which is glued on the core
The ASICs are foreseen to be produced in a 130 nm CMOS process (ABC130 [2]) with 256 channels and four rows of wire-bond pads
Summary
The flex hybrid read-out boards appropriate for the ABCN250 were developed for the petalet programme They are multi-layer flex PCBs with ASICs glued on top for readout of data and communication. For a given readout scheme either two or three different hybrid types were prototyped in the petalet project. Their layout, assembly, and electrical and mechanical test results are described in the following. Two hybrids depending on the readout scheme span across two sensors Both the lower and the one/two upper hybrids carry two rows of six ASICs each, resulting in 768 channels per row. The main functional blocks of the binary readout chip are: front-end, input register, pipeline, derandomising buffer, data compression logic blocks, command decoder, readout logic, threshold and calibration control, and power regulation
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