Design and Performance Analysis of Hybrid SELBOX Junctionless FinFET

Rajeev Pankaj Nelapati ,K Sivasankaran

doi:10.33180/infmidem2019.104

Abstract

In this work, the performance of selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure is analysed using numerical simulations. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure were studied and compared with the conventional and hybrid (or inverted-T) JLFinFETs (JLTs). The ION of the hybrid SELBOX- JLFinFET is 1.43x times better than the ION of the JLT due to the added advantage of different technologies, such as 2D-ultra-thin-body (UTB), 3D-FinFET, and SELBOX. The proposed device is modeled using sprocess and simulation study is carried using sdevice. Various analog parameters, such as transconductance (gm), transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg), and intrinsic gain (A0), are evaluated. The proposed device with a minimum feature size of 10nm exhibited better TGF, fT, VEA, and A0 in the deep-inversion region of operation.

Highlights

Silicon on insulator (SOI) MOSFETs has numerous advantages over bulk MOSFETs such as low parasitics, better isolation, radiation hardness, improved speed, ability to operate at low VDD and higher environmental temperatures [1, 2]
This paper illustrates the impact of variation in length Selbox length (LSELBOX) of the proposed structure on the ION, IOFF, sub-threshold slope (SS), drain-induced barrier lowering (DIBL), and thermal resistance
It is found from the simulation results that the proposed device architecture shows better DC performance for Lg ≈ LSELBOX

Summary

Introduction

Silicon on insulator (SOI) MOSFETs has numerous advantages over bulk MOSFETs such as low parasitics, better isolation, radiation hardness, improved speed, ability to operate at low VDD and higher environmental temperatures [1, 2]. Narayanan et al proposed a modified SOI device structure for reducing the self-heating effect [16]. In this structure, the buried oxide is patterned in the selective region under the source and drain, and not continuously, which is referred to as the SELBOX struc-. The DC and analog performance of HSJLT are evaluated and compared with conventional and hybrid JLTs. The rest of the paper is organized as follows: Section 2 discusses the process flow of the proposed device and the simulation setup. (b) (c) Figure 1: (a) Coventional JLT (SOI-JLT) (b) HJLT (c) HSJLT

Process flow and Simulation Setup

Results and Discussions

DC performance of HSJLT

Analog Performance of HSJLT

Conclusions