The Effect of Gate Stack and High-ĸ Spacer on Device Performance of a Junctionless GAA FinFET

Abstract

In this work, we investigated the effect of the gate stack and high-ĸ gate spacers on the digital and analog performance of a lightly doped n-type Si channel Junctionless Rectangular Gate All Around (JL-Re-GAA) FinFET. Different digital and analog parameters, for instance, drain current (I d ), leakage current (I off ), switching ratio (I on /I off ), subthreshold swing (SS), transconductance (g m ), output conductance (g d ), transconductance generation factor (TGF), intrinsic gain (A v ), early voltage (V EA ) have been analyzed. From the simulated results obtained, we have found that the use of gate stack and high-ĸ gate spacers remarkably improves the digital and analog figures of merits (FOMs) of the device. Thus, the JL-Re-GAA FinFET structure with high-k gate spacers and gate stack can be considered as a suitable candidate in digital and analog circuit applications.