A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance

Abstract

FinFET for system-on-chip (SoC) applications like logic/SRAM need shorter fins, whereas in analog/RF and global interconnect drivers need taller and multi-fins. To tackle this issue, we are proposing a novel bottom-spacer ground-plane (BSGP) FinFET structure. The BS helps in increasing the source-channel barrier potential by increasing BS height (BSH). The GP attributes to reducing the drain-induced barrier lowering (DIBL) and subthreshold swing (S) by grounding the source and drain electric filed owing to better gate control over the channel region. The essential process flow required for creating the BSGP FinFET structure is presented in this paper. The short-channel parameters such as ON-state current to OFF-state current (ION/IOFF) ratio, DIBL, and S are evaluated, analyzed, and compared with standard FinFET using ATLAS 3D Device simulator. In addition to that, some of the analog/RF performance metrics such as transconductance (gm), Output conductance (gd), transconductance generation factor (TGF), early voltage (VEA), intrinsic gain (AV), cut-off frequency (fT), gain transconductance frequency product (GTFP), gain frequency product (GFP) and transconductance frequency product (TFP) are extracted and compared at different BSH (=30, 40, 50 nm). It has been noticed that the proposed device is best suitable for SoC applications and future technological nodes.