Abstract
The low-power and very-high-performance 0.25 μm vertical pnp bipolar process is designed and characterized by using the mixed two-dimensional numerical device/circuit simulator (CODECS). This pnp transistor has a 25 nm-wide emitter, a 38 nm-wide base region, a current gain of 17 (without polySi emitter effect) and maximum cut-off frequency of 24 GHz. The conventional ECL circuit, designed by this pnp transistor, exhibits an unloaded gate delay of 22 psec at 1.75 mW, and a delay time less than 16 psec/stage for an unloaded ECL ring-oscillator.
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