Design and implementation of a parallel real-time FFT processor

Abstract

More and more communication systems call for an efficient FFT component. This paper implements a real-time FFT processor that performs 1 K point FFT, and, with our strategy, we realize a 16 K point FFT processor by only enlarging the memories and counter in the controller. Finally, we implemented an FFT processor with a Xilinx VirtexII FPGA, which can perform 1 K, 2 K, 4 K, 8 K and 16 K, respectively, corresponding to the external configuration. The system clock is 50 MHz, which means that our FFT processor can accomplish a 16 K complex point FFT in 40 ns.