Abstract
The analog-to-digital converter is the key component for communication and signal processing. This paper describes the design and simulations of a 3-bit flash analog-to-digital converter (ADC) which includes voltage divider network, comparators, and a priority encoder. The proposed circuit is driven by 0.6 V supply voltage with an analog input of 600 mV amplitude and 1 MHz frequency. The proposed architecture is designed, simulated, and analyzed using Cadence Virtuoso IC 6.1.5 Simulator tool in 45-nm CMOS technology. The power consumption of proposed 3-bit flash ADC is 142 uW with 12.52 nS delay and output noise of 26.55 nV/sqrt(Hz). In this paper, a high-speed, low-power CMOS flash ADC, suitable for biomedical application, is proposed and analyzed.
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