Design and characterization of submicron BiCMOS compatible high-voltage NMOS and PMOS devices

Abstract

This paper investigates the feasibility of integrating high-voltage blocking capability into a state-of-the-art submicron BiCMOS process using existing processing steps. High-voltage MOS devices fully compatible with an existing 5 V, 0.8 /spl mu/m BiCMOS process have been designed and studied through extensive two-dimensional (2-D) process and device simulations. The device layout parameters in proposed high-voltage NMOS (HV-NMOS) and high-voltage PMOS (HV-PMOS) devices are optimized to achieve highest performance possible in terms of breakdown voltage and specific on-resistance with the constraints of full process compatibility. The optimized HV-NMOS and HV-PMOS devices using minimized unit-cell pitches of 7.8 and 7.3 /spl mu/m achieved breakdown voltages of 129 V and specific on-resistances of 0.9 and 11.5 mn cm/sup 2/, respectively. Due to their full compatibility with the existing process the high-voltage MOS devices presented in this paper can be implemented without increasing manufacturing cost. The integration of the high-voltage blocking capability into the submicron BiCMOS process can expand its application field to include high-voltage input and output (I/O) functions on the same chip with high-speed analog and high-density digital signal processing circuitry.