Abstract
This paper presents the design of High-Voltage NMOS and PMOS devices with STI (shallow trench isolation) technology fully compatible with a standard 0.25 mum/5 V CMOS process technology. Breakdown voltages of 35 V for n-channel with a specific on resistance of 1.96 mOmega.cm2 and -45 V for p-channel with a specific on-resistance of 8.73 mOmega.cm2 have been achieved without any modification of existing standard CMOS process.
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