Design and characterization of high-voltage NMOS and PMOS devices in standard 0.25 μm CMOS technology

Abstract

This paper presents the design of high-voltage NMOS and PMOS devices with shallow trench isolation (STI) in standard 0.25μm/5V CMOS technology. Breakdown voltages of 20V for n-channel device with a specific on resistance of 1.06mΩcm2 and −20V for p-channel device with a specific on resistance of 2.83mΩcm2 have been achieved without any modification of existing standard CMOS process.