Deep sub-micron ESD GGNMOS layout design and optimization

Shi Jun,Hongliang Yuan,Huafeng Ding

doi:10.1051/matecconf/201819804009

Abstract

In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD devices under electrostatic pulse. Layout parameters DCGS (Drain-Contact to Gate Spacing), SCGS (Source-Contact to Gate Spacing) and BS (Substrate-source spacing) size in the paper can be used as reference for ESD GGNMOS (Gated Ground NMOS) layout design. Also this paper provides setting the DRC (Design Rule Check) command to check the distance between the N+ diffusion regions of different potentials so that ESD failure is prevented effectively. TLP (Transmission Line Pulse) current pulse signal is adopted to measure characteristics of the GGNMOS. The thesis descripts a ESD Optimal layout design from five aspects of introduction, Key elements of ESD circuits layout design, ESD layout optimization, a ESD GGNMOS layout instance and conclusion.

Highlights

There are two kinds of failures caused by ESD: One is the thermal failure caused by excessive current; the other is due to the high voltage which causes the electric effect to cause breakdown of the medium
The channel length L (Length), channel width W (Width) and even multi-finger number n of the MOS device have been determined in the GGNMOS layout design
Layout parameters DCGS, SCGS and BS size in the paper can be used as reference for ESD GGNMOS layout design

Summary

Introduction

There are two kinds of failures caused by ESD: One is the thermal failure caused by excessive current; the other is due to the high voltage which causes the electric effect to cause breakdown of the medium (such as gate oxide). The electrical failure is the ESD voltage applied directly to the vulnerable thin oxide layer, leading to dielectric breakdown or surface breakdown. A variety of reasons have led to the failure of the chip under ESD pulse. These reasons may be due to the inappropriate layout design [1], parasitic ESD devices, the internal ESD sensitive circuit structure and the incorrect placement of the power pins

Key elements of ESD circuit layout design

GGNMOS multi-finger structure and optimization of layout design parameters

ESD GGNMOS optimized layout structure

Performance after ESD layout optimization

Conclusion