Electrostatic Discharge (ESD) and latchup in advanced semiconductors

Abstract

This paper focuses on semiconductor device layout and design, design integration, digital receiver design, off-chip drivers, and ESD power clamps. The paper discussed ESD test models (HBM, MM, and CDM), ESD testing techniques, failure mechanisms, and electro-thermal models (eg. Wunsch-Bell). In addition, the section discussed ESD in diodes, and MOSFETs. This was followed on how to construct ESD circuits such as input node networks and ESD power clamps. In addition, ESD issues with receivers, off-chip drivers, and other circuitry. The paper discussed semiconductor mixed signal integration and design synthesis. In addition, the paper included RF devices, RF ESD design fundamentals, RF ESD failure mechanisms, and RF ESD circuits. RF ESD failure criteria, RF ESD testing issues, and mechanisms in both passive and active elements were discussed. The paper also discussed latchup in CMOS and BiCMOS technologies. The paper included CMOS latchup physics, latchup test structures and design, semiconductor process issues, failure analysis and design integration issues in CMOS, BiCMOS, mixed signal and smart power applications.