Analysis of ESD failure due to parasitic vertical NPN opening in integrated circuits with N-substrate process

Abstract

This paper describes the electrostatic discharge (ESD) failure caused by parasitic BJT in N-substrate process. The study of ESD failures in P-substrate process[1-3] has been a topic of increasing interest. Meanwhile N-substrate process, which may cause unexpected ESD failure, has hitherto received little attention. Through data analysis, unexpected ESD failure in N-substrate process may be attributed to parasitic vertical NPN and it is suggested that ESD failure can be improved by increasing the BVceo of parasitic vertical NPN.