A simulation study of HBM failure in an internal clock buffer and the design issues for efficient power pin protection strategy

Abstract

This paper presents the use of circuit simulations in understanding of the internal ESD (electrostatic discharge) failure observed in a 0.6 /spl mu/m CMOS technology product chip. Simulation of the ESD current paths near the V/sub dd/ pin are performed and the cause of ESD failure is identified using a circuit simulator that includes the MOS snapback models. These simulations are used to suggest issues to be considered in design of protection circuits to avoid this type of internal ESD failure.