Dead zone free area efficient Charge Pump Phase Frequency Detector in nanoscale DG-MOSFET

Abstract

In this paper, we propose the use of Double Gate MOSFET (DG-MOSFET) in the design of Charge Pump Phase Frequency Detectors (PFD)s in 32 nm and 45 nm DG MOSFET technologies. The DG-MOSFETs are used to design the universal NOR gate which is the only building block for the PFD. The DG-MOSFET NOR gate consists of half the transistor count compared to NOR gate designed in conventional CMOS. Thus 2 transistors make up the DG-MOSFET 2-input NOR gate as opposed to 4 needed in conventional CMOS. This reduction in transistor count makes the PFD area efficient. The reduced transistor count also lowers the parasitic capacitances which enhances speed. Here, we have demonstrated that for tiny phase errors of 60 ps and 80 ps the rise time of the output of a DG-MOSFET based PFD reaches the desired threshold of logic `HIGH' required to initiate the charge pump switches that follows the PFD, whereas it fails for conventional CMOS, in 32 nm and 45 nm technologies respectively. The DG-MOSFET thus finds application as a better alternative to conventional CMOS for dead zone avoidance in Phase Locked Loops.