D-CPT: a time/space efficient fault simulator

Abstract

Abstract A new fault simulation method, deductive critical path tracing (D-CPT), for very large combinational circuits is proposed. The simulator uses both the deductive fault propagation technique (used in deductive fault simulation (DFS)) and the critical path tracing (CPT) method in forming the D-CPT. Deductive fault propagation is not performed on the whole fault set of a circuit as in DFS but instead only on a partial fault set, i.e., those faults on fanout stems. The capture lines of each fanout fault are determined, and used to resolve the difficulty in determining the criticality of a fanout stem during the CPT process. Furthermore, the huge storage requirement of DFS is sharply reduced to an acceptable level when handling very large circuits. Experiments on ISCAS benchmark circuits show that the proposed method is both efficient and complete.