Exact critical path tracing fault simulation on massively parallel processor AAP2

Abstract

A fault simulation method called the fault information tracing (FIT) algorithm is presented. Although the basic concept is similar to that of the critical path tracing (CPT) method, which traces sensitive inputs backward to directly determine the fault detectability, FIT is a multiple fault propagation method which considers propagation of all possible stuck-at faults between a gate input and output. Moreover, FIT manages a 'fault information flag' which represents both fault detectability and circuit topology between the current line and a primary output. Use of the fault information flag makes it possible to greatly reduce reconvergent fanout stem analysis. Consequently, exact and efficient simulation is achieved with near linear time complexity. The FIT algorithm is described and results are presented. In addition, the FIT procedure consists of simple propagation of fault information flags between logic gates, which enable implementation on parallel processors. Its suitability for parallel processors. Its suitability for parallel processing is discussed. Moreover, a parallel fault simulation method for AAP2, a massively parallel processor system containing 65536 processing elements, is described. >