Abstract

The through-silicon via (TSV) 3D integration method has become one of the most widely used techniques for achieving system-level integration for applications that require smaller package sizes, higher interconnection density and high performance. This is because the TSV fabrication technology provides the mechanism for facilitating communications between various layers of the 3D integration system and for interconnecting stacked devices at wafer-level. Although there are several reported studies on TSV 3D integration R&D, with most of these studies focused on the improvement of TSV fabrication process, there are very limited in-depth studies associated with the TSV reliability issues and challenges. In this paper, we investigate the effect of TSV geometries on the associated TSV reliability factors. Different TSV geometries including I-type, tapered, elliptical, triangular, quadrangular and circular shapes (with same volume) are investigated to find the most reliable structure under annealing process. The results show that the tapered TSV shape releases thermo-mechanical stress more uniformly than other shapes and larger top surface shows better reliability.

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