Cost-effective and channel-scalable hardware decoders for multiple electron-beam direct-write systems

Abstract

Data throughput is a critical metric in a multiple electron-beam direct-write (MEBDW) system so that heavy-duty data processing equipment is required. The main challenge is about how to achieve high performance with cost-effective techniques. We propose a high compression rate algorithm for efficient data transfer and high speed decompression hardware to raise data throughput of the system. The hardware decoder uses pipeline architecture, a run-length encoding first-in-first-out queue, and parallel dispatch logic to increase the throughput. The decoder is evaluated on field-programmable gate array and simulated with layout images that are compressed using the proposed compression software. The results demonstrate 18.2% better compression rate and 254.8% better throughput than the previous work with similar hardware cost. Because no static random-access memory is used in the design, the channel numbers of the system can be easily scaled up, which makes it possible for the next-generation MEBDW system to achieve higher wafer per hour targets.