A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET

Abstract

The Static Random Access Memory (SRAM) has huge impact on the overall power consumption of any digital design. SRAM consumes a significant amount of power in the idle state. Therefore, the leakage power is one of the most critical metrics in SRAM designs. This paper evaluates the standby leakage power of GNRFET based 6T SRAM bitcell and compared to 10nm FinFET based 6T SRAM bitcell. It is observed that the 10nm GNRFET based SRAMs have 16.43 times less standby leakage power compared to the 10nm FinFET based SRAMs. The paper also presents an analysis of the stability and reliability of GNRFET based 6T SRAM circuit with a reduced supply voltage of 500mV. The static noise margin (SNM), which is a critical measure of SRAM stability and reliability, is determined for hold, read and write operations of the 6T GNRFET SRAM cell. Simulations were performed in HSPICE and Cadence tools.